Systematization and development of fault-tolerant PLD (FPGA, CPLD) -based decisions for embedded digital devices and systems.
Development of methods of hybrid (on-chip and off-chip) and dynamic reservation, multi-parametrical adaptation to multiple faults.
Development of modeling technique and tools for assessment, modeling, simulation and choice of PLD-based fault tolerant structures and systems that work under the impact of the space environment.
Experimental and theoretical researches of compilers and utilities for development of controlled diversity decisions for embedded dependable applications and safety-related I&C.
Theoretical and practical results
Models and architectures of fault-tolerant FPGA-based systems.
Tools and techniques for simulation and assessment of tolerance to multiple cluster faults.
Methods of multi-parametrical (threshold-structural, version-structural, space-structural, etc.) adaptation and tolerating design faults.